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 RD74LVC16240B
16-bit Buffers / Line Drivers with 3-state Outputs
REJ03D0526-0100 Rev.1.00 Mar. 14, 2005
Description
The RD74LVC16240B has sixteen inverter drivers with three state outputs in a 48 pin package. This device is a inverting buffer and has two active low enables (1G to 4G). Each enable independently controls four buffers. Low voltage and high-speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation.
Features
* * * * * * VCC = 1.65 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25C) High output current 4 mA (@VCC = 1.65 V) 8 mA (@VCC = 2.3 V) 12 mA (@VCC = 2.7 V) 24 mA (@VCC = 3.0 V to 5.5 V) * Ordering Information
Part Name RD74LVC16240BTEL Package Type TSSOP-48 pin Package Code (Previous Code) PTSP0048KA-A (TTP-48DBV) Package Abbreviation T Taping Abbreviation (Quantity) EL (1,000 pcs/reel)
Function Table
Inputs G H L L H: High level L: Low level X: Immaterial Z: High impedance A X H L Output Y Z L H
Rev.1.00 Mar. 14, 2005 page 1 of 8
RD74LVC16240B
Pin Arrangement
1G 1 1Y1 2 1Y2 3 GND 4 1Y3 5 1Y4 6 VCC 7 2Y1 8 2Y2 9 GND 10 2Y3 11 2Y4 12 3Y1 13 3Y2 14 GND 15 3Y3 16 3Y4 17 VCC 18 4Y1 19 4Y2 20 GND 21 4Y3 22 4Y4 23 4G 24
48 2G 47 1A1 46 1A2 45 GND 44 1A3 43 1A4 42 VCC 41 2A1 40 2A2 39 GND 38 2A3 37 2A4 36 3A1 35 3A2 34 GND 33 3A3 32 3A4 31 VCC 30 4A1 29 4A2 28 GND 27 4A3 26 4A4 25 3G
(Top view)
Absolute Maximum Ratings
Item Supply voltage Input diode current Input voltage Output diode current Output voltage Output current VCC, GND current / pin Storage temperature Symbol VCC IIK VI IOK VO IO ICC or IGND Tstg Ratings -0.5 to 7.0 -50 -0.5 to 7.0 -50 50 -0.5 to VCC +0.5 -0.5 to 7.0 50 100 -65 to +150 mA mA C V Unit V mA V mA VO = -0.5 V VO = VCC +0.5 V Output "H" or "L" Output "Z" or VCC:OFF VI = -0.5 V Conditions
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Rev.1.00 Mar. 14, 2005 page 2 of 8
RD74LVC16240B
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Symbol VCC VI VO Operating temperature Output current Ta IOH Ratings 1.5 to 5.5 1.65 to 5.5 0 to 5.5 0 to VCC 0 to 5.5 -40 to 85 -4 -8 -12 -24 IOL 4 8 12 24 Input rise / fall time*1 tr, tf 20 10 Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. ns/V mA C mA VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V to 5.5 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V to 5.5 V VCC = 1.65 V to 2.7 V VCC = 3.0 V to 5.5 V V Unit V Conditions Data hold At operation G, A Output "H" or "L" Output "Z" or VCC: OFF
Rev.1.00 Mar. 14, 2005 page 3 of 8
RD74LVC16240B
Electrical Characteristics
Ta = -40 to 85C Item Input voltage Symbol VIH VCC (V) 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 Output voltage VOH 1.65 to 5.5 1.65 2.3 2.7 3.0 3.0 4.5 VOL 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 Input current Output leak current Off state output current Quiescent supply current IIN IOFF IOZ ICC ICC 0 to 5.5 0 2.7 to 5.5 2.7 to 3.6 2.7 to 5.5 2.7 to 3.6 Min VCCx0.65 1.7 2.0 VCCx0.7 -- -- -- -- VCC-0.2 1.2 1.7 2.2 2.4 2.2 3.8 -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- VCCx0.35 0.7 0.8 VCCx0.3 -- -- -- -- -- -- -- 0.2 0.45 0.7 0.4 0.55 0.55 5.0 5.0 5.0 10 10 500 A A A A A VIN = 5.5 V or GND VIN/ VOUT = 5.5 V VIN = VCC or GND VO = 5.5 V or GND VIN = 3.6 V to 5.5 V VIN = VCC or GND VIN = one input at (VCC-0.6)V, other inputs at VCC or GND V IOL = 100 A IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 24 mA IOH = -24 mA V IOH = -100 A IOH = -4 mA IOH = -8 mA IOH = -12 mA V Unit V Test Conditions
Rev.1.00 Mar. 14, 2005 page 4 of 8
RD74LVC16240B
Switching Characteristics
Ta = -40 to 85C Item Propagation delay time Symbol tPLH tPHL VCC (V) 1.80.15 2.50.2 2.7 3.30.3 5.00.5 Output enable time tZH tZL 1.80.15 2.50.2 2.7 3.30.3 5.00.5 Output disable time tHZ tLZ 1.80.15 2.50.2 2.7 3.30.3 5.00.5 Between output pins skew*
1
From Unit ns A (Input) Y
To (Output)
Min 1.0 1.0 1.0 1.5 1.0 1.0 1.0 1.0 1.5 1.0 1.0 1.0 1.0 1.5 1.0 -- -- -- -- -- -- --
Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4.0 8.0
Max 10.9 7.9 6.2 5.5 4.5 12.6 9.6 7.7 7.0 6.0 12.1 7.8 7.7 7.0 6.0 -- -- -- 1.0 1.0 -- --
ns
G
Y
ns
G
Y
tOSLH tOSHL
1.80.15 2.50.2 2.7 3.30.3 5.00.5
ns
Input capacitance Output capacitance Note:
CIN CO
3.3 3.3
pF pF
1. This parameter is characterized but not tested. tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|
Operating Characteristics
Ta = 25C Item Power dissipation Capacitance Symbol CPD VCC (V) 1.8 2.5 3.3 5.0 Min -- -- -- -- Typ 25.0 25.0 27.0 32.0 Max -- -- -- -- Unit pF Test conditions f = 10 MHz
Rev.1.00 Mar. 14, 2005 page 5 of 8
RD74LVC16240B
Test Circuit
VCC VCC
1G to 4G
Output RL S1 OPEN V TT GND
See Function Table
Input
1Y1 to 4Y4 CL 1A1 to 4A4 RL
Pulse generator Zout = 50
Symbol t PLH / t PHL t ZH/ t HZ t ZL / t LZ
S1 OPEN GND V TT
Note:
1. CL includes probe and jig capacitance.
Waveforms - 1
tf Input A 90 % Vref tr 90 % 10 % t PLH Output Y Vref 10 % Vref GND t PHL VOH Vref VOL VIH
Notes:
1. Input waveform : PRR = 10 MHz, ZO = 50 , duty cycle 50%
Rev.1.00 Mar. 14, 2005 page 6 of 8
RD74LVC16240B Waveforms - 2
tf Input G 90 % Vref 10 % t ZL Waveform - A t ZH Waveform - B Vref Vref t HZ VOH - V tr 90 % Vref 10 % t LZ VIH GND 1/2VTT VOL + V VOL VOH GND INPUTS VCC (V)
VCC = 1.80.15 V VCC = 2.50.2 V VCC = 2.7 V VCC = 3.30.3 V VCC = 5.00.5 V
VI
VCC VCC
tr/tf
Vref
VTT
CL
30 pF 30 pF 50 pF 50 pF 50 pF
RL
1.0 k 500 500 500 500
V
0.15 V 0.15 V 0.3 V 0.3 V 0.3 V
2 ns 1/2 VCC 2x VCC 2 ns 1/2 VCC 2x VCC
1.5 V 1.5 V 6V 6V
2.7 V 2.5 ns 2.7 V 2.5 ns VCC
2.5 ns 1/2 VCC 2x VCC
Notes:
1. Input waveform : PRR = 10 MHz, ZO = 50 , duty cycle 50% 2. Waveform - A shows input conditions such that the output is "L" level when enable by the output control. 3. Waveform - B shows input conditions such that the output is "H" level when enable by the output control.
Rev.1.00 Mar. 14, 2005 page 7 of 8
RD74LVC16240B
Package Dimensions
JEITA Package Code P-TSSOP48-6.1x12.5-0.50 RENESAS Code PTSP0048KA-A Previous Code TTP-48DBV MASS[Typ.] 0.2g
*1
D F 25
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
48
bp
HE
E
c
Index mark
Reference Symbol
Dimension in Millimeters Min Nom 12.5 6.10 Max 12.7
*2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
24 bp L1 x M
A1 A bp b1 c c
1
0.08
0.13
0.18 1.20
0.14
0.19
0.24
0.10
0.15
0.20
HE
0 7.90 8.10 0.50
8 8.30
A
A1
y L
e x y
0.08 0.10 0.65 0.4
1
Detail F
Z L L 0.5 1.0
0.6
Rev.1.00 Mar. 14, 2005 page 8 of 8
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
http://www.renesas.com
(c) 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon 2.0


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